Real DV engineering, worked all the way through.

A series on building AI-native tooling for chip design verification, from understanding why LLMs fail, through entity extraction, local model evaluation, fine-tuning, and knowledge graphs.

A practical series on verifying control and status registers with UVM RAL, beyond what the built-in sequences catch, and the patterns real SoC projects need.

Using UVM's built-in region allocator for shared memory across block, subsystem, and SoC testbenches, and where the built-in class needs a wrapper to actually scale.

The testbench architecture problems that show up specifically when a block-level environment has to survive being integrated into a subsystem and then a full SoC.

The firmware-on-RTL problems that only show up at multi-core and regression scale: races existing debug tools can't localize, a message-ID logging scheme built to replace UART streaming, and what survives the jump to emulation, post-silicon, and SoC integration.